1. Field of the Invention
The present invention relates to a semiconductor device, and in particular to an X-ray sensor with both a diode and a transistor present on the same Silicon On Insulator (SOI) substrate.
2. Related Art
For a sensor of SOI construction, there is a proposal for a CMOS imaging sensor including, on a an Silicon On Insulator (SOI) substrate, a photodiode and a amplification transistor for amplifying a signal from charge photoelectric converted using a silicon substrate and accumulated in the diode (see Japanese Patent Application Laid-Open (JP-A) No. 2002-124657).
In an X-ray sensor, methods employed to raise detection sensitivity during X-ray irradiation include employing a low impurity concentration and high resistance substrate and applying a bias of several hundred volts to the back face of the substrate in order to deplete the entire substrate. FIG. 17 is a schematic vertical cross-section for explaining a conventional X-ray sensor 9. In a conventional device, generally, when depleting an N-type substrate 100, a high impurity concentration P-type diffusion layer 114, serving as the anode of the diode configured in the low impurity concentration N-type substrate 100, is connected to earth 180, a high impurity concentration N-type diffusion layer 102 serving as the cathode of the diode and an electrode 120 on the back face of the N-type substrate 100 are connected to a anode 172 of the power source 170. A reverse voltage is then applied to the diode. In order to relax the electrical field when this is performed in the depletion layer spreading out to the anode electrode high impurity concentration P-type diffusion layer 114 side, a low impurity concentration P-well diffusion layer 112 is formed so as to cover the high impurity concentration P-type diffusion layer 114, thereby raising the reverse voltage withstanding ability of the diode.
However, there is a limit to the electric field relaxing effect obtained by the P-well diffusion layer 112 and breakdown occurs when the depletion layer spreading out to the low impurity concentration P-well diffusion layer 112 side reaches the high impurity concentration P-type diffusion layer 114 when voltage is applied to PN junction, due to the intense electric field occurring at the edge of the high impurity concentration P-type diffusion layer 114. The large potential difference within the P-well diffusion layer 112 also causes problems from the perspective of withstand voltage.